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19-5135; Rev 0; 1/10
TION KIT EVALUA BLE ILA AVA
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
General Description
The MAX17085B is an all-in-one notebook power solution integrating a multichemistry battery charger, dual fixedoutput Quick-PWMK step-down controllers, and dual keep-alive linear regulators: Charger: The high-frequency (~1.4MHz) multichemistry battery charger uses a current-mode, fixed inductor current ripple architecture that significantly reduces component size and cost. Low-offset sense amplifiers allow the use of low-value sense resistors for charging and input current limit. The charger uses n-channel switching MOSFETs. Adjustable charge current, charge voltage, and cell selection allow for flexible use with different battery packs. Charge current is set by an analog control input, or a PWM input. High-accuracy current-sense amplifiers provide fast cycle-by-cycle current-mode control to protect against short circuits to the battery and respond quickly to system load transients. Additionally, the charger provides a high-accuracy analog output that is proportional to the adapter current. An integrated charge pump controls an n-channel adapter selector switch. The charge pump remains active even when the charger is off. When the adapter is absent, a p-channel MOSFET selects the battery. Main SMPS: The dual Quick-PWM step-down controllers with synchronous rectification generate the 5V and 3.3V main power in a notebook. Lowside MOSFET sensing provides a simple low-cost, highly efficient valley current-limit protection. The MAX17085B also includes output undervoltage, output overvoltage, and thermal-fault protection. Separate enable inputs for each SMPS and a combined open-drain power-good output allow flexible power sequencing. Voltage soft-start reduces inrush current, while passive shutdown discharges the output through an internal switch. Fast transient response, with an extended on-time feature reduces output capacitance requirements. Selectable pulseskipping mode and ultrasonic mode improve lightload efficiency. Ultrasonic mode operation maintains a minimum switching frequency at light loads, minimizing audible noise effects. Dual LDO Regulators: An internal 5V/100mA LDO5 with switchover can be used to either generate the 5V bias needed for power-up or other lower power "always-on" suspend supplies. Another 3.3V/50mA LDO3 provides "always-on" power to a system microcontroller.
Features
S All-in-One Charger Plus Dual Main Step-Down Controllers S 5V/100mA and 3.3V/50mA LDO Regulators S Main Dual Quick-PWM with Fast Transient Response and Extended On-Time 300kHz to 800kHz Switching Frequency Fixed 5V and 3.3V SMPS Outputs Low-Noise Ultrasonic Mode Autoretry Fault Protection S Charger High Switching Frequency (1.4MHz) Selectable 2-, 3-, and 4-Cell Battery Voltage Automatic Selection of System Power Source Internal Charge-Pump for Adapter n-Channel MOSFETs Drive Q0.4% Accurate Charge Voltage Q2.5% Accurate Input Current Limiting Q3% Accurate Charge Current S Monitor Outputs for AC Adapter Current (Q2% Accuracy) Battery Discharge Current (Q2% Accuracy) AC Adapter OK S Analog/PWM (100Hz to 500kHz) Adjustable Charge Current Setting S AC Adapter Overvoltage and Overcurrent Protection
MAX17085B
Applications
Notebook Computers PDAs and Mobile Communicators 5V and 3.3V Supplies 2-to-4, Li+-Cell, Battery-Powered Devices
Ordering Information
PART MAX17085BETL+ TEMP RANGE -40C to +85C PIN-PACKAGE 40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
ABSOLUTE MAXIMUM RATINGS (Note 1)
TON, DCIN, CSSP, BATT, CSIP to GND, LX_ to GND ........................................................-0.3V to +28V CSIP to CSIN, CSSP to CSSN ..............................-0.3V to +0.3V LDO3, LDO5, VCC to GND (Note 2) .......................-0.3V to +6V ISET, VCTL, ACIN, ACOK to GND ..........................-0.3V to +6V OUT3, OUT5 to GND (Note 2) ................................-0.3V to +6V ON3, ON5, PGOOD to GND ...................................-0.3V to +6V ILIM3, ILIM5, SKIP, REF to GND .............. -0.3V to (VCC + 0.3V) GND to EP ............................................................-0.3V to +0.3V DL_ to EP...............................................-0.3V to (VLDO5 + 0.3V) BST_ to GND .........................................................-0.3V to +34V BST_ to LDO5........................................................-0.3V to +28V DH3 to LX3 ............................................ -0.3V to (VBST3 + 0.3V) BST3 to LX3.............................................................-0.3V to +6V DH5 to LX5 ............................................ -0.3V to (VBST5 + 0.3V) BST5 to LX5.............................................................-0.3V to +6V DHC to LXC ........................................... -0.3V to (VBSTC + 0.3V) PDSL to GND .......................................................-0.3V to + 36V BSTC to LXC ...........................................................-0.3V to +6V CELLS, CC, IINP to GND ......................-0.3V to (VLDO5 + 0.3V) LDO_ Short Circuit to GND ....................................... Momentary LDO5 Current (Internal Regulator) Continuous............. +100mA LDO3 Current (Internal Regulator) Continuous............... +50mA LDO_ Current (Switched Over) Continuous .................. +200mA Continuous Power Dissipation (TA = +70NC) 40-Pin Thin QFN (derate 34.5mW/NC above +70NC) 2857mW Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Soldering Temperature (reflow) ......................................+240NC
Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit. Note 2: LDO5 has a weak leakage to VCC when LDO5 is more than 0.5V above VCC. OUT5 has a weak leakage to VCC when OUT5 is more than 0.5V above VCC.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER INPUT SUPPLIES Adapter Present Quiescent Current Charging IDCIN + ICSSP + ICSSN, enabled ON3 = ON5 = SKIP = VCC, VOUT3 = 3.5V, VOUT5 = 5.3V Charging disabled VISET = 2.4V, IDCIN + ICSSP + ICSSN, IINP ON ON3 = ON5 = SKIP = VCC, VOUT3 = 3.5V, VOUT5 = 5.3V VISET = GND VCSSP = VCSSN = 24V, TA = +25C VBATT = 16.8V, adapter absent, TA = +25C VBATT = 2V to 19V, adapter present IDCIN ON3 = ON5 = SKIP = VCC, charger disabled; VOUT3 = 3.5V, VOUT5 = 5.3V DCIN = 5V to 24V, ON3 = ON5 = GND ICC ON3 = ON5 = SKIP = VCC, charger disabled; VOUT3 = 3.5V, VOUT5 = 5.3V Note: LDO5 is NOT guaranteed to be in regulation until DCIN is above 6V. 4.5 200 0.1 130 1.0 3 1.5 1.5 1.2 0.1 6 mA 2.5 2.5 2.2 2 4 650 0.2 270 1.5 24 FA FA mA FA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
Adapter Absent Quiescent Current CSSN Input Current BATT + CSIP + CSIN + LXC Input Current DCIN Input Current DCIN Standby Supply Current VCC Supply Current DCIN Input Voltage Range
mA
2
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DCIN Undervoltage-Lockout Trip Point for Charger DCIN POR Threshold VCC Undervoltage Lockout Threshold VCC POR Threshold LINEAR REGULATORS VLDO5 LDO_ Output-Voltage Accuracy VLDO3 Internal LDO Voltage After Switchover LDO3 Short-Circuit Current LDO5 Short-Circuit Current LDO5 Bootstrap Switch Resistance LDO3 Bootstrap Switch Resistance Thermal-Shutdown Threshold REFERENCE REF Output Voltage REF Undervoltage-Lockout Threshold MAIN SMPS OUT5 Output Voltage Accuracy OUT3 Output Voltage Accuracy Load Regulation Error Line Regulation Error VOUT5 VOUT3 IN = 6V to 28V, SKIP = REF IN = 6V to 28V, SKIP = REF Either SMPS, SKIP = 2V, ILOAD = 0 to 5A Either SMPS, SKIP = GND, ILOAD = 0 to 5A Either SMPS, SKIP = VCC, ILOAD = 0 to 5A Either SMPS, IN = 6V to 28V IN = 12V, VOUT5 = 5.0V (Note 3) RTON = 202kI (800kHz + 10%) RTON = 549kI (300kHz + 10%) 1073 402 5.033 3.267 5.083 3.300 -0.1 -1.7 -1.5 0.005 1263 473 1452 ns 545 %/V % 5.135 3.333 V V VREF VREF_UVLO IREF = 50FA REF falling 2.09 2.10 2.0 2.11 V V tSHDN VLDO5 VLDO3 DCIN = 6V to 24V, ON5 = ON3 = GND 0mA < ILDO5 < 100mA, ON5 = GND LDO5 = 5V, ILDO5 = 0 0mA < ILDO3 < 50mA, ON3 = GND Not production tested Not production tested LDO3 = GND LDO5 = GND LDO5 to OUT5, VOUT5 = 5V, ILDO5 = 50mA LDO3 to OUT3, VOUT3 = 3.3V, ILDO3 = 50mA Hysteresis = 50NC 4.90 3.23 4.4 2.7 50 100 1.0 1.5 +160 5.00 3.30 4.5 2.8 5.10 V 3.37 4.6 2.9 130 260 2.5 3 V mA mA I I NC SYMBOL VDCIN(UVLO) VDCIN(POR) VCC(UVLO) VDCIN falling VDCIN rising Falling edge of DCIN Falling edge of VCC, PWM disabled below this threshold Rising edge of VCC Falling edge of VCC 3.8 CONDITIONS MIN 7.0 TYP 7.2 7.7 2.0 4.0 4.2 1.5 V 4.3 7.9 MAX UNITS V V V
MAX17085B
DH5 On-Time
tON5
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3
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS RTON = 549kI (300kHz - 10%) IN = 12V, VOUT3 = 3.3V (Note 3) RTON = 202kI (800kHz - 10%) (Note 3) Duty cycle > 50%; not for production test tSS Rising edge on ON_ 15 fSW(USONIC) SKIP = GND MIN 866 325 210 TYP 1019 382 270 300 2 22 MAX 1171 ns 439 330 360 ns ns ms kHz UNITS
DH3 On-Time
tON3
Minimum Off-Time Extended On-Time Blanking Soft-Start Time Ultrasonic Operating Frequency OUT_ Overvoltage Trip Threshold (PGOOD Pulled Low Above This Level) OUT_Overvoltage Fault Propagation Delay OUT_ Undervoltage Protection Trip Threshold OUT_ Output Undervoltage Fault Propagation Delay PGOOD Lower Trip Threshold PGOOD Propagation Delay PGOOD Output Low Voltage MAIN SMPS FAULT DETECTION
tOFF(MIN)
With respect to error comparator threshold
13
16
19
%
tOVP
FB_ forced 50mV above trip threshold With respect to error comparator threshold 65
10 70 10 75
Fs % Fs -150 mV Fs 0.3 V
tUVP With respect to error comparator threshold, falling edge, hysteresis = 15mV tPGOOD OUT5 or OUT3 forced 50mV beyond PGOOD trip threshold, falling edge PGOOD low impedance, ON5 = ON3 = GND, ISINK = 4mA IPGOOD PGOOD high impedance, SMPS in regulation, PGOOD forced to 5.5V, TA = +25C 7 0.2 TA = +25C VILIM_ = 0.5V VLIM_ (VAL) VAGND - VLX_ VILIM_ = 1.00V VILIM_ = 2.10V INEG(US) VZX VAGND - VLX_, SKIP = VCC or GND, VILIM = 1V -0.1 40 87 184 -350
-250 10
PGOOD Leakage Current Fault Reset Timer MAIN SMPS CURRENT LIMIT ILIM_ Adjustment Range ILIM_ Leakage Current Valley Current-Limit Threshold (Adjustable) Ultrasonic Negative Current-Limit Threshold Current-Limit Threshold (Zero Crossing)
1 10 2.1 +0.1 50 100 210 72 1.5 60 113 236
FA ms V FA mV
mV mV
4
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS High = SKIP Mid = PWM Low = ultrasonic VSKIP = 0 or 5V, TA = +25C High (SMPS on) Low (SMPS off) VON3 = VON5 = 0 or 5V, TA = +25C RDSCHG ON_ = GND -2 7.5 20 MIN 2.3 1.5 0 -2 2.4 0.8 +2 50 TYP MAX VCC 1.9 0.8 +2 UNITS MAIN SMPS INPUTS AND OUTPUTS SKIP Threshold Voltage SKIP Leakage Current ON_ Input Logic Levels ON_ Leakage Current OUT_ Discharge-Mode On-Resistance SMPS GATE DRIVERS DH3, DH5 Gate Driver On-Resistance DL3, DL5 Gate Driver On-Resistance DH3, DH5 Gate Driver Source/ Sink Current DL3, DL5 Gate Driver Source Current DL3, DL5 Gate Driver Sink Current DHC Gate Driver OnResistance DLC Gate Driver On-Resistance Internal BST_ Switch On-Resistance BST_ Leakage Current CHARGER SMPS DHC Off-Time K Factor Sense Voltage for Minimum Discontinuous Mode Ripple Current Zero Crossing Comparator Threshold Cycle-by-Cycle Current- Limit Sense Voltage VDCIN = 19V, VBATT = 10V VCSIP - VCSIN VCSIP - VCSIN VCSIP - VCSIN 120 30 35 5 10 125 130 40 ns/V mV mV mV BST3 - LX3 and BST5 - LX5 forced to 5V; high state BST3 - LX3 and BST5 - LX5 forced to 5V; low state DL3, DL5; high state DL3, DL5; low state DH3, DH5 forced to 2.5V, BST3 - LX3 and BST5 - LX5 forced to 5V 1.6 1.6 1.5 0.6 2 1.7 3.3 1.5 0.8 3 3 5 2 20 3 2.1 6 6 3.8 I 3.8 3.5 1.5 I A A A I I I FA VSKIP V FA V FA I
MAX17085B
RDH3, RDH5
RDL3, RDL5 IDH
IDL(SOURCE) DL3, DL5 forced to 2.5V IDL(SINK) RDHC RDLC RBST IBST DL3, DL5 forced to 2.5V High state, IDHC = 10mA Low state, IDHC = -10mA High state, IDLC = 10mA Low state, IDLC = -10mA IBST_ = 10mA, VDD = 5V VBST_ = 24V, OUT3 and OUT5 above regulation threshold, TA = +25C
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5
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS CELLS = open, VCTL = REF, 2 cells VBATT CELLS = GND, VCTL = REF, 3 cells CELLS = LDO3, VCTL = REF, 4 cells CELLS = open, 2 cells VCTL = GND or VCTL = REF, TA = +25C CELLS = open MIN -0.5 -0.5 -0.5 1.0 -1 1.9 2.8 CELLS = GND or CELLS = 3.6V, TA = +25C -2 +2 2.1 TYP MAX +0.5 +0.5 +0.5 3.5 +1 0.8 2.3 V FA V V V FA % UNITS CHARGE-VOLTAGE REGULATION Battery-Regulation Voltage Accuracy VCTL Range VCTL Input Bias Current CELLS 3-Cell Threshold CELLS 2-Cell Level CELLS 4-Cell Threshold CELLS Input Bias Current CHARGE-CURRENT REGULATION ISET Range Full-Charge-Current Accuracy (CSIP to CSIN) Trickle Charge-Current Accuracy Charge-Current Gain Error Charge-Current Offset Error CSIP/CSIN/BATT Input-Voltage Range CSIP Leakage Current CSIN Leakage Current ISET Power-Down Mode Threshold ISET Input Bias Current ISET PWM Threshold ISET Frequency ISET Effective Resolution INPUT SOURCE-CURRENT REGULATION Input Source Current-Limit Threshold CSSP/CSSN Input-Voltage Range 6 VCSS VCSSP - VCSSN 58.5 -2.5 5 60.0 61.5 +2.5 26 mV % V fISET fISET = 100kHz VISET-SDN VCSIP = VCSIN = 24V, TA = +25C VCSIP = VCSIN = 24V, TA = +25C ISET falling ISET rising VISET = REF/2 and VISET = REF, TA = +25C ISET rising ISET falling 0.8 0.128 8 500 Based on VISET = REF and VISET = 0.6 x REF Charging current, analog setting VBATT = 4V to 16.8V VISET = REF, or PWM = 100% VISET = 0.6 x REF, or PWM = 60% 0 97 57.6 1.25 -1.5 -1.4 0 -0.2 1 20 32 -0.15 26 38 100 60.0 2.70 REF 103 mV 62.4 4.30 +1.5 +1.4 24 +0.2 4 32 46 +0.15 2.4 mV % mV V FA FA mV FA V kHz Bit V
VCSI
VCSI
VBATT = 4V to 16.8V, VISET = REF/36 or PWM = 2.7%
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER IINP Current-Sense Amplifier Voltage Gain IINP Output-Voltage Range VCSSP - VCSSN = 60mV IINP Accuracy VCSSP - VCSSN = 40mV VCSSP - VCSSN = 20mV IINP Gain Error IINP Offset Error Measured at VCSSP - VCSSN = 60mV and VCSSP - VCSSN = 20mV Measured at VCSSP - VCSSN = 60mV and VCSSP - VCSSN = 20mV VCSIN-OCP With respect to VCSSP _VCSSN SYMBOL GIINP CONDITIONS MIN 59.1 0 -2 -3 -4 -1.25 -0.6 78 130 16 When ACOCP comparator is high and at the time the blanking time expires 0.6 TYP 60.0 MAX 60.9 4 +2 +3 +4 +1.25 +0.6 % mV mV % ms s % UNITS V/V V
MAX17085B
ADAPTER OVERCURRENT (ACOC) DETECTION ACOCP Threshold ACOCP Blanking Time ACOCP Waiting Time ACIN, ACOK, AND ACOV ACIN Rising Debounce ACIN Falling Delay ACIN Input Bias Current ACOK Detect Threshold ACOV Detect Threshold ACOK Sink Current ACOK Leakage Current ADAPTER PRESENT DETECTION Adapter Absence Detect Threshold Adapter Detect Threshold CHARGE-PUMP MOSFET DRIVER PDSL Gate-Driver Source Current PDSL Gate-Driver Output Voltage High PDSL SWITCH CONTROL PDSL Turn-Off Resistance BATTERY OVERVOLTAGE BATT Overvoltage Threshold VCELL(OV) VBATT rising, hysteresis = 20mV (typ) +100 mV/cell RPDSL Measured from PDSL to GND 2.5 kI IPDSL-SRC VPDSL-H VPDSL - VDCIN = 3V, VDCIN = 19V VDCIN = 19V VDCIN + 5.3 60 VDCIN +8 FA V VACINOK VACINOV TA = +25C Measured at ACIN rising, hysteresis = 40mV (typ) Measured at ACIN rising, hysteresis = 40mV (typ) VACOK = 0.4V, VACIN = 1.7V VACOK = 5.5V, VACIN = 1.3V, TA = +25C VDCIN - VBATT, VDCIN falling VDCIN - VBATT, VDCIN rising 0 300 100 440 -1 1.47 -2 2.05 -2.38 1 1 2.10 1.50
44 10 +1 1.53 +2 2.15 +2.38
ms Fs FA V % V % mA FA
200 600
mV mV
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7
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = -40C to +85C, unless otherwise noted.) (Note 4) PARAMETER INPUT SUPPLIES Adapter Present Quiescent Current IDCIN + ICSSP + ICSSN, ON3 = ON5 = SKIP = VCC, VOUT3 = 3.5V, VOUT5 = 5.3V IDCIN + ICSSP + ICSSN, ON3 = ON5 = SKIP = VCC, VOUT3 = 3.5V, VOUT5 = 5.3V VCSSP = VCSSN = 24V VBATT = 16.8V, adapter absent VBATT = 2V to 19V, adapter present IDCIN ON3 = ON5 = SKIP = VCC, charger disabled; VOUT3 = 3.5V, VOUT5 = 5.3V DCIN = 5V to 24V, ON3 = ON5 = GND ICC ON3 = ON5 = SKIP = VCC, charger disabled; VOUT3 = 3.5V, VOUT5 = 5.3V Note: LDO5 is NOT guaranteed to be regulation until DCIN is above 6V VDCIN(UVLO) VCC(UVLO) VDCIN falling VDCIN rising Falling edge of VCC, PWM disabled below this threshold DCIN = 6V to 24V, ON5 = ON3 = GND, 0mA < ILDO5 < 100mA, ON5 = GND LDO5 = 5V, ILDO5 = 0, 0mA < ILDO3 < 50mA, ON3 = GND LDO3 = GND LDO5 = GND VREF VOUT5 VOUT3 IREF = 50FA IN = 6V to 28V, SKIP = REF IN = 6V to 28V, SKIP = REF IN = 12V, VOUT5 = 5.0V (Note 3) RTON = 549kI (300kHz + 10%) RTON = 202kI (800kHz + 10%) 2.08 5.008 3.25 1073 402 3.8 4.5 6.9 7.9 4.3 Charging enabled Charging disabled VISET = 2.4V, IINP ON VISET = GND 6 mA 2.5 2.5 mA 2.2 2 4 650 0.2 300 1.5 24 mA FA mA V V V FA SYMBOL CONDITIONS MIN TYP MAX UNITS
Adapter Absent Quiescent Current CSSN Input Current BATT + CSIP + CSIN + LXC Input Current DCIN Input Current DCIN Standby Supply Current VCC Supply Current DCIN Input-Voltage Range DCIN Undervoltage-Lockout Trip Point for Charger VCC UndervoltageLockout Threshold LINEAR REGULATORS VLDO5 LDO_ Output-Voltage Accuracy VLDO3 LDO3 Short-Circuit Current LDO5 Short-Circuit Current REFERENCE REF Output Voltage MAIN SMPS OUT5 Output-Voltage Accuracy OUT3 Output-Voltage Accuracy
FA
4.85 3.20
5.15 V 3.40 130 260 2.12 5.160 3.35 1452 ns 545 mA mA V V V
DH5 On-Time
tON5
8
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = -40C to +85C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL IN = 12V, VOUT3 = 3.3V (Note 3) (Note 3) Duty cycle > 50%; not for production test fSW(USONIC) SKIP = GND 13 CONDITIONS RTON = 549kI (300kHz - 10%) RTON = 202kI (800kHz - 10%) MIN 866 325 TYP MAX 1171 ns 439 330 360 ns ns kHz UNITS
MAX17085B
DH3 On-Time
tON3
Minimum Off-Time Extended On-Time Blanking Ultrasonic Operating Frequency MAIN SMPS FAULT DETECTION OUT_ Overvoltage Trip Threshold (PGOOD Pulled Low Above this Level) OUT_ Undervoltage Protection Trip Threshold PGOOD Lower Trip Threshold PGOOD Output Low Voltage Fault Reset Timer MAIN SMPS CURRENT LIMIT ILIM_ Adjustment Range Valley Current-Limit Threshold (Adjustable)
tOFF(MIN)
With respect to error comparator threshold
12
20
%
With respect to error comparator threshold With respect to error comparator threshold, falling edge, hysteresis = 15mV PGOOD low impedance, ON5 = ON3 = GND, ISINK = 4mA Not for production test
63 -350
77 -150 0.4
% mV V ms
7 0.2 2.1 60 115 246 VCC 1.9 0.8 +2 0.8
V mV
VILIM_ = 0.5V VLIM_ (VAL) VAGND - VLX_ VILIM_ = 1.00V VILIM_ = 2.10V High = SKIP
40 85 174 2.3 1.5 0 -2 2.4
MAIN SMPS INPUTS AND OUTPUTS SKIP Threshold Voltage SKIP Leakage Current ON_ Input Logic Levels SMPS GATE DRIVERS DH3, DH5 Gate Driver OnResistance DL3, DL5 Gate-Driver OnResistance DHC Gate-Driver On-Resistance RDH3, RDH5 BST3 - LX3 and BST5 - LX5 forced to 5V; high state BST3 - LX3 and BST5 - LX5 forced to 5V; low state DL3, DL5; high state DL3, DL5; low state High state, IDHC = 10mA Low state, IDHC = -10mA 3.8 I 3.8 3.5 1.5 3 2.1 I I VSKIP Mid = PWM Low = ultrasonic VSKIP = 0 or 5V, TA = +25C High (SMPS on) Low (SMPS off) V FA V
RDL3, RDL5 RDHC
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9
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = -40C to +85C, unless otherwise noted.) (Note 4) PARAMETER DLC Gate-Driver On-Resistance CHARGER SMPS DHC Off-Time K Factor Cycle-by-Cycle Current-Limit Sense Voltage CHARGE-VOLTAGE REGULATION Battery-Regulation Voltage Accuracy VCTL Range CELLS 3-Cell Threshold CELLS 2-Cell Level CELLS 4-Cell Threshold CHARGE-CURRENT REGULATION ISET Range Full-Charge-Current Accuracy (CSIP to CSIN) Charging current, analog setting VISET = REF, or PWM = 100% VISET = 0.6 x REF, or PWM = 60% 0.0 97 57.6 1.2 -1.5 Based on VISET = REF and VISET = 0.6 x REF -1.4 0 VISET-SDN ISET falling ISET rising ISET rising ISET falling fISET 0.8 0.128 500 20 32 REF 103 mV 62.4 4.3 +1.5 +1.4 24 32 46 2.4 mV % mV V mV V kHz V CELLS = open 1.9 2.8 CELLS = open, VCTL = REF, 2 cells VBATT CELLS = GND, VCTL = REF, 3 cells CELLS = LDO3, VCTL = REF, 4 cells -0.5 -0.5 -0.5 0 +0.5 +0.5 +0.5 2.4 0.8 2.3 V V V V % VDCIN = 19V, VBATT = 10V VCSIP - VCSIN 30 120 40 130 ns/V mV SYMBOL RDLC CONDITIONS High state, IDLC = 10mA Low state, IDLC = -10mA MIN TYP MAX 6 6 UNITS I
VCSI
VBATT = 4V to 16.8V
Trickle Charge-Current Accuracy Charge-Current Gain Error Charge-Current Offset Error CSIP/CSIN/BATT Input Voltage Range ISET Power-Down Mode Threshold ISET PWM Threshold ISET Frequency
VCSI
VBATT = 4V to 16.8V, VISET = REF/36 or PWM = 2.7%
10
_____________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO5, LDO3, OUT5, OUT3, and REF, VCC = 5V, ON3 = ON5 = VCC, VDCIN = VLXC = VCSSP = VCSSN = 19V, VBSTC - VLXC = 5V, VBATT = VCSIP = VCSIN = 12.6V, VVCTL = VISET = 1.8V, CELLS = open, TA = -40C to +85C, unless otherwise noted.) (Note 4) PARAMETER Input Source-Current Limit Threshold CSSP/CSSN Input-Voltage Range IINP Current-Sense Amplifier Voltage Gain IINP Output-Voltage Range VCSSP - VCSSN = 60mV IINP Accuracy VCSSP - VCSSN = 40mV VCSSP - VCSSN = 20mV IINP Gain Error IINP Offset Error ACIN, ACOK, AND ACOV ACOK Detect Threshold ACOV Detect Threshold ACOK Sink Current ADAPTER PRESENT DETECTION Adapter Absence Detect Threshold Adapter Detect Threshold CHARGE-PUMP MOSFET DRIVER PDSL Gate-Driver Output Voltage High VPDSL_H VDCIN = 19V VDCIN + 5.3 V VACINOK VACINOV Measured at ACIN rising, hysteresis = 40mV (typ) Measured at ACIN rising, hysteresis = 40mV (typ) VACOK = 0.4V, VACIN = 1.7V VDCIN - VBATT, VDCIN falling VDCIN - VBATT, VDCIN rising 1.47 -2 2.05 -2.38 1 0 300 200 600 1.53 +2 2.15 +2.38 V % V % mA mV mV Measured at VCSSP - VCSSN = 60mV and VCSSP - VCSSN = 20mV Measured at VCSSP - VCSSN = 60mV and VCSSP - VCSSN = 20mV GIINP SYMBOL CONDITIONS MIN 58.5 -2.5 5 59.9 0 -2 -3 -4 -1.5 -0.65 TYP MAX 61.5 +2.5 26 60.1 4 +2 +3 +4 +1.5 +0.65 % mV % UNITS mV % V V/V V INPUT SOURCE-CURRENT REGULATION VCSS VCSSP - VCSSN
MAX17085B
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds. Note 4: Specifications to TA = -40C are guaranteed by design and not production tested.
______________________________________________________________________________________
11
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Typical Operating Characteristics
(Circuit of Figure 1, VADP = VSYS = 20V, VBATT = 16.8V, LDO5 = VCC = 5V, LDO3 = 3.3V, TA = +25C, unless otherwise noted.)
IINP ERROR vs. SYSTEM CURRENT (DC SWEEP)
MAX17085B toc01
CHARGER-CURRENT ERROR vs. BATTERY VOLTAGE
MAX17085B toc02
CHARGER CURRENT vs. ISET SETTING (ANALOG)
8 CHARGER CURRENT (A) 7 6 5 4 3 2 1 0 VADAPTER = 19V 4A INPUT CURRENT LIMIT 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ISET VOLTAGE (V) 4-CELL 3-CELL
MAX17085B toc03
0 -1 -2 IINP ERROR (%) -3 -4 -5 -6 -7 -8 -9 -10 0 10 20 30 40 50 60 70 ADAPTER ABSENT, VBATTERY = 13V VADAPTER = 19V
0.6 0.5 CHARGER-CURRENT ERROR (%) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 ICHARGER = 3A ICHARGER = 4A ICHARGER = 5A
9 2-CELL
80
-0.3 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 BATTERY VOLTAGE (V)
VCSSP - VCSSN (mV)
CHARGER CURRENT vs. ISET SETTING (PWM)
MAX17085B toc04
CHARGER-VOLTAGE PER CELL vs. VCTL VOLTAGE
MAX17085B toc05
CHARGER-VOLTAGE ERROR vs. CELL VOLTAGE
0.33 CHARGER-VOLTAGE ERROR (%) 0.31 0.29 0.27 0.25 0.23 0.21 0.19 0.17 0.15 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 CELL VOLTAGE (V) 4-CELL 3-CELL 2-CELL
MAX17085B toc06 MAX17085B toc09 MAX17085B toc08
7 6 CHARGER CURRENT (A) 5 4 3 2 1 0 0 VADAPTER = 19V 3-CELL BATTERY RS2 = 10mI 4A INPUT CURRENT LIMIT
7 6 CHARGER VOLTAGE (V) 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 VADAPTER = 19V 3-CELL BATTERY RS2 = 10mI 2.5 3.0
0.35
10 20 30 40 50 60 70 80 90 100 ISET DUTY CYCLE (%)
3.5
VCTL VOLTAGE (V)
CHARGER SWITCHING FREQUENCY vs. BATTERY VOLTAGE
MAX17085B toc07
CHARGER VOLTAGE ERROR vs. CHARGER CURRENT
0.25 2-CELL CHARGER VOLTAGE ERROR (%) 0.20 0.15 3-CELL 0.10 0.05 0 4-CELL VADAPTER = 19V 4A INPUT CURRENT LIMIT 0 1 2 3 4 5 6 CHARGER CURRENT (A) 0V 27.5V 19V
BATTERY REMOVAL (VBATT = 3V)
PDSL 5V/div DCIN 5V/div VBATT 5V/div
1.6 CHARGER SWITCHING FREQUENCY (MHz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 3 6 VADAPTER = 19V ICHARGER = 3A 3-CELL BATTERY 9 12
0A 3-CELL BATTERY 100s/div
ILCHG 2A/div
15
BATTERY VOLTAGE (V)
12
_____________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VADP = VSYS = 20V, VBATT = 16.8V, LDO5 = VCC = 5V, LDO3 = 3.3V, TA = +25C, unless otherwise noted.)
MAX17085B
BATTERY REMOVAL (VBATT = 11V)
MAX17085B toc10
SYSTEM LOAD TRANSIENT (0A 3A 0A )
CC 1V/div VBATT 5V/div DCIN 5V/div
MAX17085B toc11
CHARGER OUTPUT SHORT CIRCUIT
MAX17085B toc12
1.5V
1.5V 12.6V
CC 1V/div VBATT 2V/div ISYSLD 2A/div ILCHG 2A/div
11V 19V
0A
0V
VBATT 5V/div
0A 3-CELL BATTERY 100s/div
ILCHG 2A/div
0A
19V ADAPTER INPUT 3-CELL BATTERY, 3A CHARGING CURRENT 400s/div
0A 3-CELL BATTERY 20s/div
ILCHG 2A/div
POWER-SOURCE SELECTOR SCHEME WHEN BATTERY IS PRESENT (ADAPTER REMOVAL)
MAX17085B toc13
POWER-SOURCE SELECTOR SCHEME WHEN BATTERY IS PRESENT (ADAPTER INSERTION)
VBATT 5V/div 12.6V VSYSLD 12.6V 10V/div
MAX17085B toc14
VREF LINE REGULATION (SWITCHING AND NOT SWITCHING)
SWITCHING 2.098 REF VOLTAGE (V) 2.096 NOT SWITCHING 2.094 2.092
MAX17085B toc15
12.6V 20V
VBATT 5V/div VSYSLD 10V/div PDSL 20V/div
2.100
0V 20V
PDSL 20V/div
0V VADAPTER 10V/div
20V ADAPTER INPUT, 3-CELL BATTERY 10ms/div
VADAPTER 0V 10V/div
20V ADAPTER INPUT, 3-CELL BATTERY 10ms/div
2.090 4
CHARGER AND SMPSs ARE ALL ON WHEN SWITCHING, ALL OFF WHEN NOT SWITCHING 8 12 16 20 24 28
INPUT VOLTAGE (V)
VREF vs. AMBIENT TEMPERATURE
MAX17085B toc16
CHARGER EFFICIENCY vs. CHARGING CURRENT
MAX17085B toc17
LDO5 LOAD REGULATION
MAX17085B toc18
2.110 2.108 2.106 REF VOLTAGE (V) 2.104 2.102 2.100 2.098 2.096 2.094 0 10 20 30 40 50 60 70
98 96 94 EFFICIENCY (%) 92 90 88 86 84 82 VADAPTER = 20V 4A INPUT CURRENT LIMIT 0 1 2 3 4 5 6 7
5.10 5.05 LDO5 VOLTAGE (V) 5.00 4.95 4.90 4.85 4.80 VADAPTER = 19V CHARGER OFF SMPS5 AND SMPS3 OFF LDO3 NO LOAD 0 20 40 60 80 100 120
4-CELL 3-CELL 2-CELL
80
8
140
AMBIENT TEMPERATURE (C)
CHARGING CURRENT (A)
LOAD CURRENT (mA)
______________________________________________________________________________________
13
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VADP = VSYS = 20V, VBATT = 16.8V, LDO5 = VCC = 5V, LDO3 = 3.3V, TA = +25C, unless otherwise noted.)
LDO3 LOAD REGULATION
MAX17085B toc19
LDO5 vs. AMBIENT TEMPERATURE
4.988 4.987 LDO5 VOLTAGE (V) 4.986 4.985 4.984 4.983 4.982 4.981 4.980 4.979
MAX17085B toc20
LDO3 vs. AMBIENT TEMPERATURE
3.300 3.299 LDO3 VOLTAGE (V) 3.298 3.297 3.296 3.295 3.294 3.293 3.292
MAX17085B toc21
3.40 3.35 3.30 3.25 3.20 3.15 3.10 0 VADAPTER = 19V CHARGER OFF SMPS5 AND SMPS3 OFF 10 20 30 40 50
4.989
3.301
LDO3 VOLTAGE (V)
60
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
LOAD CURRENT (mA)
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
LDO AND REF POWER-UP
MAX17085B toc22
DCIN, LDO AND REF POWER REMOVAL
DCIN 10V/div LDO3 2V/div LDO5 2V/div REF 1V/div 19V
MAX17085B toc23
LDO5 LOAD TRANSIENT (0mA 100mA 0mA)
MAX17085B toc24
0V 0V
3.3V 5V
DCIN 10V/div 0V LDO3 2V/div
LDO5 (AC) 100mV/div
0V 0V
2.1V
LDO5 2V/div REF 1V/div 0A ON3 = ON5 = GND 4s/div ILDO5 100mA/div
2ms/div
2ms/div
LDO3 LOAD TRANSIENT (0mA 50mA 0mA)
MAX17085B toc25
SMPS5 EFFICIENCY vs. LOAD CURRENT (CHARGER AND SMPS3 ARE OFF)
MAX17085B toc26
SMPS5 EFFICIENCY vs. LOAD CURRENT (CHARGER AND SMPS3 ARE OFF)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 ULTRASONIC MODE SKIP MODE PWM MODE
MAX17085B toc27
100 95
LDO3 (AC) 100mV/div
100
0V
90 85 80 75 70 65 60 55 50 0.01 0.1 1 LOAD CURRENT (A) 7V 12V
20V
0A ON3 = ON5 = GND 4s/div
ILDO3 50mA/div
EFFICIENCY (%)
SKIP MODE PWM MODE 10
55 50 0.01 0.1 1 LOAD CURRENT (A)
12V INPUT 10
14
_____________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VADP = VSYS = 20V, VBATT = 16.8V, LDO5 = VCC = 5V, LDO3 = 3.3V, TA = +25C, unless otherwise noted.)
MAX17085B
SMPS3 EFFICIENCY vs. LOAD CURRENT (CHARGER AND SMPS5 ARE OFF)
MAX17085B toc28
SMPS3 EFFICIENCY vs. LOAD CURRENT (CHARGER AND SMPS5 ARE OFF)
MAX17085B toc29
SMPS5 OUTPUT vs. LOAD CURRENT
MAX17085B toc30
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.01 0.1 1 LOAD CURRENT (A) SKIP MODE PWM MODE 7V 12V 20V
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50
SKIP MODE
5.20
PWM MODE
OUTPUT VOLTAGE (V)
5.15
ULTRASONIC MODE
5.10
SKIP MODE
5.05
PWM MODE
ULTRASONIC MODE 12V INPUT 0.01 0.1 1 LOAD CURRENT (A) 10
5.00 0.01 0.1 1 LOAD CURRENT (A)
12V INPUT
10
10
SMPS3 OUTPUT vs. LOAD CURRENT
MAX17085B toc31
SMPS5 STARTUP AND SHUTDOWN LOAD
MAX17085B toc32
SMPS5 STARTUP WAVEFORMS (SWITCHING REGULATOR)
MAX17085B toc33
3.35 3.34 OUTPUT VOLTAGE (V) 3.33 3.32 3.31 3.30 3.29 3.28 0.01 0.1 1 LOAD CURRENT (A)
ULTRASONIC MODE
0V
ON5 5V/div
ON5 5V/div 0V OUT5 2V/div
SKIP MODE
0V OUT5 2V/div 0V PGOOD 5V/div IL5 5A/div 400s/div
PWM MODE
5V
LDO5 0V 200mV/div 0A 2ms/div
12V INPUT
10
SMPS5 SHUTDOWN WAVEFORMS (SWITCHING REGULATOR)
MAX17085B toc34
SMPS5 LOAD TRANSIENT (1A 4A 1A)
MAX17085B toc35
SMPS3 LOAD TRANSIENT (1A 4A 1A)
MAX17085B toc36
5V 5V ON5 5V/div 1A 5V OUT5 2V/div PGOOD 5V/div IL5 0A 5A/div 400s/div 10s/div
IOUT5 2A/div 1A OUT5 3.3V 100mV/div
IOUT3 2A/div OUT3 100mV/div
5V
0A
IL5 2A/div
0A 10s/div
IL3 2A/div
______________________________________________________________________________________
15
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Pin Description
PIN 1 NAME LX3 FUNCTION Inductor Connection for SMPS3. Connect LX3 to the switched side of the inductor. LX3 is the lower supply rail for the DH3 high-side gate driver. Boost Flying Capacitor Connection for SMPS3. Connect to an external capacitor as shown in Figure 1. An optional resistor in series with BST3 allows the DH3 turn-on current to be adjusted. A 4.7 resistor is recommended to improve crosstalk between SMPSs. Low-Side Gate-Driver Output for SMPS3. DL3 swings from PGND to LDO5. Output Voltage-Sense Input for SMPS3. OUT3 is an input to the Quick-PWM on-time one-shot timer. OUT3 also serves as the feedback input for the preset 3.3V, and the discharge path when in shutdown. When OUT3 is in regulation, LDO3 is internally set to a lower level, and a bypass switch between OUT3 and LDO3 is enabled. 3.3V Linear Regulator Output. LDO3 is the output of the 3.3V linear regulator supplied from LDO5. LDO3 is switched over to OUT3 when SMPS3 is in regulation plus 200Fs. Bypass LDO3 to PGND with a 4.7FF or greater ceramic capacitor. LDO5 Supply Input. Bypass DCIN with a 1FF capacitor to PGND. 5V Linear Regulator Output. LDO5 provides the power to the MOSFET drivers. LDO5 is the output of the 5V linear regulator supplied from DCIN. LDO5 is switched over to OUT5 when SMPS5 is in regulation plus 200Fs. Bypass LDO5 to PGND with a 4.7FF or greater ceramic capacitor. Output Voltage-Sense Input for SMPS5. OUT5 is an input to the Quick-PWM on-time one-shot timer. OUT5 also serves as the feedback input for the preset 5V, and the discharge path when in shutdown. When OUT5 is in regulation, LDO5 is internally set to a lower level, and a bypass switch between OUT5 and LDO5 is enabled. Low-Side Gate-Driver Output for SMPS5. DL5 swings from PGND to LDO5. Boost Flying Capacitor Connection for SMPS5. Connect to an external capacitor as shown in Figure 1. An optional resistor in series with BST5 allows the DH5 turn-on current to be adjusted. A 4.7 resistor is recommended to improve crosstalk between SMPSs. Inductor Connection for SMPS5. Connect LX5 to the switched side of the inductor. LX5 is the lower supply rail for the DH5 high-side gate driver. High-Side Gate-Driver Output for SMPS5. DH5 swings from LX5 to BST5. Low-Side Power MOSFET Driver Output for Charger. Connect to the low-side n-channel MOSFET gate. Boost Flying Capacitor Connection for Charger. Connect a 0.1FF capacitor from BSTC to LXC, and a Schottky diode from LDO5 to BSTC. High-Side Driver Source Connection. Connect a 0.1FF capacitor from BSTC to LXC. High-Side Power MOSFET Driver Output for Charger. Connect to high-side n-channel MOSFET gate. Open-Drain Power-Good Output for SMPS3 and SMPS5. PGOOD is low when either SMPS3 or SMPS5 output voltage is more than 250mV (typ) below the nominal regulation threshold, during soft-start, in shutdown (ON3 = ON5 = GND), and after either fault latch has been tripped. After the soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation plus 200Fs. When only one SMPS is active, PGOOD monitors the active SMPS output. When the 2nd SMPS is started, PGOOD is blanked high-Z during the 2nd SMPS soft-start plus 200Fs, then PGOOD monitors both SMPS outputs.
2 3
BST3 DL3
4
OUT3
5 6 7
LDO3 DCIN LDO5
8
OUT5
9 10
DL5 BST5
11 12 13 14 15 16
LX5 DH5 DLC BSTC LXC DHC
17
PGOOD
16
_____________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Pin Description (continued)
PIN 18 19 20 21 22 23 24 NAME ACOK CSIN CSIP BATT PDSL CSSN CSSP FUNCTION AC-Detect Output. This open-drain output is low impedance when ACIN is greater than 1.5V, with a delay of 44ms. The ACOK output remains high impedance when the MAX17085B is powered down. Connect a 100kI pullup resistor from LDO3 or LDO5 to ACOK. Output Current-Sense Negative Input Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN. Battery Voltage Feedback Input Power Source Switch Driver Output. When the adapter is not present or an overvoltage and overcurrent event is detected, the PDSL output is pulled to GND. Leave PDSL unconnected when it is not used. Input Current-Sense Negative Input Input Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN. Input Current Monitor Output. IINP sources the current proportional to the current sensed across CSSP and CSSN. The gain from (CSSP - CSSN) to IINP is 60V/V: VIINP = 60 x (VCSSP - VCSSN) IINP also monitors the battery-discharge current when the adapter is absent. To monitor the discharge current, set ISET above the PWM threshold. Pull ISET to GND to disable the IINP batterydischarge current mode. Trilevel Input for Setting Number of Cells: U CELLS = open; charge with 2 times the cell voltage programmed at VCTL. U CELLS = GND; charge with 3 times the cell voltage programmed at VCTL. U CELLS > 2.8V; charge with 4 times the cell voltage programmed at VCTL. Charger Loop-Compensation Point. External compensation node for the charge voltage and input current-limit loops. Connect a 4.7nF to 47nF capacitor to GND. Typically a 10nF capacitor works for most applications. AC Adapter Detect Input. ACIN is the input to an uncommitted comparator. The ACIN threshold is 1.7V for ACOK and 2.1V for ACOVP. When the ACIN threshold is above ACOK and below the ACOVP threshold, then PDSL is enabled. Cell Charge Voltage-Control Input. VCTL range is from GND to LDO5. For 4.375V/cell setting, connect VCTL to REF: VCELL = 2.083 x VVCTL Analog Supply Voltage Input. Connect VCC to the system supply voltage with a series 47I resistor, and bypass to analog ground using a 1FF or greater ceramic capacitor. Dual-Mode Input for Setting Maximum Charge Current. In PWM mode, use input frequencies from 128Hz to 500kHz for charge-current setting. If there are no two edges within 20ms, ISET is directly used as an analog input. In analog mode, charge current is set as follows: 31 ISET
MAX17085B
25
IINP
26
CELLS
27
CC
28
ACIN
29 30
VCTL VCC
I CHG =
Pull ISET to GND to shut down the charger.
100mV VISET x RS2 VREF
32 33 34 35
REF GND ILIM3 ILIM5
2.1V Voltage Reference and Device Power-Supply Input. Bypass REF with a 1FF capacitor to GND. Analog Ground Valley Current-Limit Adjustment for SMPS3. The GND - LX3 current-limit threshold is 1/10 the voltage present on ILIM3 over a 0.2V to 2.1V range. Valley Current-Limit Adjustment for SMPS5. The GND - LX5 current-limit threshold is 1/10 the voltage present on ILIM5 over a 0.2V to 2.1V range. 17
______________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Pin Description (continued)
PIN NAME FUNCTION Pulse-Skipping Control Input. This tri-level input determines the operating mode for the switching regulators. High (VCC) = pulse-skipping mode Mid (1.8V) = forced-PWM operation GND = ultrasonic mode Switching Frequency Setting Input. An external resistor between the input power source and this pin sets the nominal switching frequency according to the following equation: fSW(NOM) = 1/(CTON x (RTON + 6.5kI)) 37 TON where CTON = 6pF. SMPS5 has a switching frequency that is 10% higher than nominal, and SMPS3 has a switching frequency 10% lower than nominal. RTON is high impedance when ON3 = ON5 = GND. Enable Input for SMPS3. Drive ON3 high to enable SMPS3. Drive ON3 low to shut down SMPS3. Enable Input for SMPS5. Drive ON5 high to enable SMPS5. Drive ON5 low to shut down SMPS5. High-Side Gate-Driver Output for SMPS3. DH3 swings from LX3 to BST3. Exposed Pad. Internally connected to power ground (PGND). Connect the backside exposed pad to the system power ground as well.
36
SKIP
38 39 40 --
ON3 ON5 DH3 EP
Standard Application Circuit
The MAX17085B standard application circuit (Figure 1) features a 4A charger, 8A outputs on SMPS5 and
SMPS3, and a 100mA LDO5 and 50mA LDO3 typical of most notebook CPU applications. See Table 1 for component selections. Table 2 lists the component suppliers.
Table 1. Component Selection for Standard Applications
COMPONENT Input Voltage Input Capacitor SMPS3: 3.3V, 8A, 500kHZ VSYS = 7V to 24V (2) 10FF, 25V Taiyo Yuden TMK432BJ106KM Murata GRM31CR61E106K COUT3 (1) 100FF, 6V, 18mI SANYO 6TPE100MI L3 1.5FH, 2.1mI, 11.8A Sumida CEP125S-1R5 NH3 13A, 9.4mI/12mI, 30V Fairchild FDS6298 NL3 13A, 7.2mI/10mI, 30V Fairchild FDS6670A 0.45V (45mV limit) RILIM3A = 66.5kI RILIM3B = 82.5kI SMPS5: 5V, 8A, 600kHZ VSYS = 7V to 24V (2) 10FF, 25V Taiyo Yuden TMK432BJ106KM Murata GRM31CR61E106K COUT5 (1) 100FF, 6V, 18mI SANYO 6TPE100MI L5 1.5FH, 2.1mI, 11.8A Sumida CEP125S-1R5 NH5 13A, 9.4mI/12mI, 30V Fairchild FDS6298 NL5 13A, 7.2mI/10mI, 30V Fairchild FDS6670A 0.45V (45mV limit) RILIM5A = 66.5kI RILIM5B = 82.5kI CHARGER, 16.8V, 4A, 1.2MHZ VADP = 18V to 20V (2) 4.7FF, 25V Taiyo Yuden TMK432BJ475KM Murata GRM31CR71E475M COUT(CHG) (1) 4.7FF, 25V Taiyo Yuden TMK432BJ475KM Murata GRM31CR71E475M LCHG 2FH, 19mI, 4.5A Sumida CDR7D28MN-2R0 NHC 6.6A, 17mI/25mI, 30V International Rectifier IRF7807D1PBF NLC 6.6A, 17mI/25mI, 30V International Rectifier IRF7807D1PBF --
Output Capacitor
Inductor
High-Side MOSFET
Low-Side MOSFET
Current-Limit Setting
18
_____________________________________________________________________________________
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Q1b Q1a AC ADAPTER VADP N3 R4 150kI C7 10nF RS1 15mI SYSTEM POWER RAIL VSYS
N4 CDCIN 1FF N4 PROVIDES REVERSE ADAPTER PROTECTION. REPLACE WITH DIODE IF REVERSE ADAPTER PROTECTION IS NOT NEEDED. RACIN1 6 DCIN 22
51.1kI 24 CSSP 23 CSSN DHC BSTC RACIN2 28 29 32 ACIN VCTL REF CSIP GND CSIN 26 31 CELLS ISET CC 27 CCC 10nF BATT IINP 11 9 LX5 DL5 37 21 25 CIINP 0.1FF RTON 300kI VSYS 40 2 1 3 RBST3 4.7I CBST3 0.1FF L3 1.5FH NH3 CIN3 2 x 10FF 25V 20 19 DCSIP* RCSIN* 10I LXC DLC 16 14 15 13 CNLC 1nF RCSIP* 5I RS2 10mI VBATT BATTERY POWER RAIL COUT(CHG) 4.7FF RBATT* 10I SYSTEM CURRENT MONITOR BATTERY CBSTC 0.1FF RELEARN 5V LDO NH(CHG) CIN(CHG) N5 2 x 4.7FF PDSL
NL(CHG)
LCHG 2FH
CELLS OPEN GND 5V PWM SIGNAL VSYS CIN5 2x 10FF 25V
COUNT 2 3 4
CREF 1FF
33
NH5 L5 1.5FH CBST5 0.1FF RBST5 4.7I
12 10
DH5 BST5
MAX17085B
+5V, 8A COUT5 100FF
D5**
NL5
TON
8 5V LDO 100mA R1 47I CVCC 1.0FF RILIM5A RILIM5B 35 18 17 R2 100kI 3.3V LDO 50mA R3 100kI 5 CLDO3 4.7FF 7 CLDO5 4.7FF 30 REF
OUT5 LDO5
DH3 BST3
VCC
LX3 DL3
+3.3V, 8A COUT3 100FF
NL3
D3**
ILIM5 ACOK PGOOD
OUT3
4 REF RILIM3A
ADAPTER OK POWER-GOOD
ILIM3 SKIP LDO3 ON3 ON5 PAD
34 36 38 39 RILIM3B POWER GROUND
ON OFF
ANALOG GROUND
*COMPONENTS REQUIRED FOR PROTECTION FROM HARD SHORTS ON BATT TO PGND. **COMPONENTS REQUIRED FOR PROPER OPERATION. DO NOT REMOVE.
Figure 1. Standard Application Circuit ______________________________________________________________________________________ 19
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Table 2. Component Suppliers
SUPPLIER AVX Corp. Central Semiconductor Corp. Fairchild Semiconductor International Rectifier KEMET Corp. NEC/TOKIN America Panasonic Corp. Philips/nxp Semiconductor Pulse Engineering WEBSITE www.avxcorp.com www.centralsemi.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokinamerica.com www.panasonic.com/industrial www.semiconductors.philips.com www.pulseeng.com SUPPLIER Renesas Technology Corp. SANYO Electric Co., Ltd. Sumida Corp. Taiyo Yuden TDK Corp. TOKO America, Inc. Vishay (Dale, Siliconix) Wurth Elektronik GmbH & Co. KG WEBSITE www.renesas.com www.sanyodevice.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.vishay.com www.we-online.com
Detailed Description
The MAX17085B integrated charger and main stepdown controllers are ideal for notebook applications where board space and solution cost are key requirements. Together with the integrated, always-on 100mA LDO5 and 50mA LDO3, the MAX17085B provides a complete power solution for the notebook in the off-state, standby-state, and full active state. A functional diagram of the MAX17085B is shown in Figure 2. The MAX17085B uses a new thermally optimized highfrequency architecture that reduces the output capacitance and inductance, resulting in smaller PCB area and lower cost. The MAX17085B charger includes all the necessary functions to charge Li+, NiMH, and NiCd batteries. An all n-channel synchronous-rectified stepdown DC-DC converter is used to implement a precision constant-current, constant-voltage charger. The charge current and input current-limit sense amplifiers have lowinput offset errors (200FV typ), allowing the use of smallvalued sense resistors. The 5V and 3.3V main SMPSs in the MAX17085B use Maxim's Quick-PWM pulse-width modulator, specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constanton-time and constant-off-time PWM schemes.
20
Charger
The MAX17085B includes a high-current (100mA), always-on fixed 5V linear regulator (LDO5). LDO5 is required to generate the 5V bias supply necessary to power up the switching regulators, and as the input supply to the 3.3V linear regulator (LDO3). Once the 5V switching regulator (SMPS5) is enabled and in regulation, LDO5 is bypassed by an internal switch from OUT5 to LDO5. After switchover, the LDO5 pin can source 200mA. LDO5 starts up as soon as DCIN has valid voltage (around 2.5V), and regulates to ~ 4.5V using an internal crude reference. REF starts at the same time, and once REF is in regulation, LDO5 switches over to use the accurate REF, and regulates up to 5V. The MAX17085B requires a low-noise 5V bias supply (VCC) for its internal circuitry. Typically, this 5V bias is supplied by LDO5 through a lowpass filter. The total supply current required for the MAX17085B is: IBIAS(MAX) = ICC(MAX) + fSW5QG5 + fSW3QG3 + fSWCQGC 45mA to 90mA (typ) A lower current (50mA), always-on fixed 3.3V linear regulator, is also included in the MAX17085B. Once the 3.3V switching regulator (SMPS3) is enabled and in regulation, LDO3 is bypassed by an internal switch from OUT3 to LDO3. After switchover, the LDO3 pin can source more than 200mA. LDO3 starts up as soon as REF is in regulation. This limits the inrush current by sequencing LDO5 to start before LDO3.
100mA 5V Linear Regulator (LDO5) and Bias Supply (VCC)
Main SMPS
50mA, 3.3V Linear Regulator (LDO3)
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Thermal-Fault Protection (tSHDN) The MAX17085B features a thermal fault-protection circuit. When the junction temperature rises above +160NC, a thermal sensor activates the fault latch, pulls PGOOD low, enables the 20I discharge circuit, and disables the controller--DH and DL pulled low. After the junction temperature cools by 50NC, the controller automatically restarts. This protects the internal LDO when a sustained overcurrent or output short circuit occurs.
When VCC rises above the power-on reset (POR) threshold, the MAX17085B clears the fault latches and resets the soft-start circuit, preparing the controller for power-up. However, the VCC undervoltage-lockout (UVLO) circuitry inhibits switching until VCC reaches its 4.2V (typ) UVLO threshold.
CSSP IINP CSSN CURRENTSENSE AMP TOFF BLOCK ACOV LDO5 SKIP
POR, UVLO
When VCC drops below the UVLO threshold (falling edge), the controller stops switching, pulling DH and DL low. When the 1.5V POR falling edge threshold is reached, the DL state no longer matters since there is not enough voltage to force the switching MOSFETs into a low on-resistance state, so the controller pulls DL high, allowing a soft discharge of the output capacitors (damped response). However, if the VCC recovers before reaching the falling POR threshold, DL remains low until the error comparator has been properly powered up and triggers an on-time. When DCIN is high enough for LDO5 to be in regulation and VCC to be above its UVLO, the main SMPS can begin running. Charger operation requires DCIN to be above its 7.7V UVLO threshold.
MAX17085B
PDSL CHARGE PUMP SMPS3 DRIVER BLOCK
ON3 ILIM3 DH3 BST3 LX3 DL3 OUT3
DCIN
BATT DHC BSTC LXC DLC CC CSIP CSIN ISET VCTL CELLS ACIN ACOK VCC REF GND
DRIVER
LVC BLOCK
LDO3 LDO5
LDO3 DCIN LDO5
CURRENTSENSE AMP
MAX17085B TON ADJUST TON OUT5 TON BLOCK ACOV LDO5 SKIP DRIVER OUT5 FB REF ON5 DH5 BST5 LX5 DL5 ILIM5 SKIP OUT5 OUT3 PAD PGOOD LOGIC PGOOD
VBATT
AC COMP
REF
Figure 2. Functional Diagram ______________________________________________________________________________________ 21
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Charger Detailed Description
The MAX17085B charger has three regulations loops: a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). The loops operate independently of each other. The CCV voltage-regulation loop monitors BATT to ensure that its voltage never exceeds the voltage set by VCTL and CELLS. The CCI battery charge current-regulation loop monitors current delivered to BATT to ensure that it never exceeds the current limit set by ISET. The charge current-regulation loop is in control as long as the battery voltage is below the set point. When the battery voltage reaches its set point, the voltage-regulation loop takes control and maintains the battery voltage at the set point. A third loop (CCS) takes control and reduces the charge current when the adapter current exceeds the input current limit. The CCI current loop is internally compensated while the CCS and CCV loops are externally compensated with a capacitor at the CC pin. The new thermally optimized high-frequency architecture controls the power dissipation in the high-side MOSFET, resulting in reduced output capacitance and inductance. The MAX17085B features separate control inputs to set the per-cell voltage and the number of cells in series. The VCTL input sets the per-cell voltage, while the CELLS input sets the total number of cells in series. Together, these two inputs set the charge voltage at the BATT input, providing a flexible way to support different cell types and different battery-pack configurations. Setting the Per-Cell Charge Voltage (VCTL) The MAX17085B supports charge voltages of 4.0V/cell to 4.4V/cell based on the following equation: VBATT Cell = 2.083 x VCTL The dynamic range of the VCTL input is limited, so it is possible to achieve 0.5% charge voltage accuracy using resistive voltage-dividers composed of 1% accurate resistors. Figure 3 shows a simple method to set two different CELL voltages using a logic output from the embedded controller. Connecting VCTL to REF = 2.10V, which gives 4.375V/cell. Setting the Number of Cells (CELLS) The trilevel CELLS input allows simple switching between 2, 3, and 4 cells in series. The ISET input controls the voltage across current-sense resistor RS2. ISET can accept either analog or digital inputs. The full-scale differential voltage between CSIP and CSIN is 100mV (5A for RS2 = 20mI). Important: Keep ISET low during the initial power-up of the MAX17085B. Wait 10ms to allow PDSL to reach its final voltage before enabling the battery charger. Analog ISET When the MAX17085B powers up and the charger is ready, if there are no two clock edges within 20ms, the circuit assumes ISET is an analog input, and disables the PWM filter block. For ISET analog input, set ISET according to the following equation: I CHG = 100mV VISET x RS2 VREF
Setting Charge Current (ISET)
The input range for ISET is from 0 to REF. To shut down the charger, pull ISET below 26mV.
Setting the Charge Voltage
VCELL (H) = 2.083 O VCELL (L) = 2.083 O
VREF O R2 R1 + R2
VREF O R2//R3 R1 + R2//R3 REF R1 VCTL
MAX17085B
R3 VCTL CONTROL
R2
Figure 3. VCTL Setting
Table 3. CELLS Pin Setting
CELLS PIN VOLTAGE OPEN GND > 2.8V CELLS COUNT 2 3 4 SETTING Charge with 2 times the cell voltage programmed at VCTL Charge with 3 times the cell voltage programmed at VCTL Charge with 4 times the cell voltage programmed at VCTL
22
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Digital ISET If there are two clock edges on ISET within 20ms, the PWM filter is enabled and ISET accepts digital PWM input. The PWM filter accepts the digital signal with a frequency from 128Hz to 500kHz. Zero duty cycle shuts down the MAX17085B, and the 99% duty cycle corresponds to full scale (100mV) across CSIP and CSIN. The PWM filter has a DAC with 8-bit resolution that corresponds to equivalent VCSIP - VCSIN steps. Each step is:
VSTEP = VREF = 0.391mV (7.8mA with RS2 = 20m) 256 21
AC Adapter Overcurrent (ACOC) When the input current is 1.3 times the input current-limit setting, PDSL is pulled to GND after a 16ms blanking time. This turns off the adapter switch and enables the battery selector switch. After 0.6s, PDSL is reenabled. If the fault condition persists, the cycle is repeated, until the third time when the charger is latched off. To clear the fault latch, remove the adapter and allow DCIN to fall below its UVLO threshold before reinserting the adapter. Analog Input Current-Monitor Output IINP monitors the system-input current, which is sensed across CSSP and CSSN. The voltage at IINP is proportional to the input current: VIINP = GIINP x I ADP x RS1 VIINP = 60 x (VCSSP - VCSSN ) where IADP is the DC current supplied by the AC adapter, GIINP is the transconductance of the sense amplifier (60V/V typ), and RS1 is the resistor connected between CSSP and CSSN. When the adapter is absent, drive ISET above 2.1V to enable IINP during battery discharge.
MAX17085B
Choose a current-sense resistor (RS2) to have a sufficient power dissipation rating to handle the full-charge current. The current-sense voltage may be reduced to minimize the power dissipation period. However, this may degrade accuracy due to the current-sense amplifier's input offset (200V). See the Typical Operating Characteristics to estimate the charge-current accuracy at various set points.
Input Source Current
Setting Input Current Limit The total input current, from a wall adapter or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the controller decreases the charge current to provide priority to system load current. System current normally fluctuates as portions of the system are powered up or down. The input-current-limit circuit reduces the power requirement of the AC wall adapter, which reduces adapter cost. As the system supply rises, the available charge current drops linearly to zero. Thereafter, the total input current can increase without limit. The total input current can be estimated as follows: I x VBATT IINPUT = ILOAD + CHG VADP x where E is the efficiency of the DC-to-DC converter (typically 85% to 95%). In the MAX17085B, the voltage across CSSP and CSSN is constant at 60mV. Choose the current-sense resistor, RS1, to set the input current limit. For example, for 4A input current limit choose RS1 = 15mI. For the input current-limit settings, which cannot be achievable with standard sense resistor values, use a resistive voltagedivider between CSSP and CSSN to tune the setting.
The ACIN input goes to two internal comparators, one for adapter detection (ACOK) and another for adapter overvoltage detection (ACOV). When ACIN is above 1.5V, the open-drain ACOK output becomes low impedance after 44ms. When ACIN rises above 2.1V, the MAX17085B detects an ACOV condition and immediately pulls PDSL to GND, turning off the adapter selection switch and enabling the battery selector switch. This protects the system rail from excessively high voltages that might violate the absolute maximum ratings of the downstream components. Note that ACOK remains low even when ACIN is above the ACOV threshold. Use a resistive voltage-divider from the adapter's output to the ACIN pin to set the appropriate detection threshold. Connect a 100kI pullup resistor between LDO3 or LDO5 and ACOK. The MAX17085B integrates a charge pump to drive the gate of n-channel adapter selector switches (N3 and Q1a) and the p-channel battery-selector switch (Q1b). When the adapter is present, PDSL is driven 8V above VDCIN so that N3 and Q1a are on, and Q1b is off. See the Operating Conditions section for the definition of adapter present.
23
AC Adapter Detection (ACIN, ACOK, ACOV)
Automatic Power-Source Selection (PDSL)
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Table 4. Charger Operating Mode Truth Table
DCIN X X < UVLO < UVLO < UVLO ADAPTER PRESENT (NOTE 5) No No Yes Yes Yes INPUT CURRENT VCSSP - VCSSN X X > OCP threshold X < OCP threshold ACIN X X X VACIN > VACINOV VACINOK < VACIN and VACIN < VACINOV VACINOK < VACIN and VACIN < VACINOV X VACINOK < VACIN and VACIN < VACINOV < ACOV threshold ISET < 1V > 1V X X X PDSL GND GND GND GND VDCIN + 8V CHARGER STATE OFF OFF OFF OFF OFF IINP OFF ON ON ON ON COMMENTS -- -- -- -- --
> UVLO
Yes
X
X
GND
OFF
ON
Adapter overvoltage fault Adapter overcurrent fault ISET shutdown
> UVLO
Yes
> OCP threshold
X < ISET shutdown threshold > ISET shutdown threshold
GND VDCIN + 8V VDCIN + 8V
OFF
ON
> UVLO
Yes
< OCP threshold
OFF
ON
> UVLO
Yes
< OCP threshold
ON (ISET control)
ON
--
Note 5: Adapter is present when VDCIN - VCSIN > 420mV with VDCIN rising, and absent when VDCIN - VCSIN < 120mV with VDCIN falling.
When the adapter voltage is removed and the adapter is absent, the charger is disabled and PDSL is pulled to GND. N3 and Q1a turn off, and Q1b turns on to supply power to the system from the battery. Table 4 defines the MAX17085B charger operating conditions.
The operation of the DC-to-DC controller is determined by the following five comparators as shown in the functional diagram in Figures 2 and 4: U The IMIN comparator triggers a pulse in discontinuous mode when the accumulated error is too high. IMIN compares the control signal (LVC) against 5mV (typ) (referred at VCSIP - VCSIN). When LVC is less than 5mV, DHC and DLC are both forced low. Indirectly, IMIN sets the peak inductor current in discontinuous mode. U The CCMP comparator is used for current-mode regulation in continuous conduction mode. CCMP compares LVC against the inductor current. The highside MOSFET on-time is terminated when the CSI voltage is higher than LVC. U The IMAX comparator provides a secondary cycleby-cycle current limit. IMAX compares CSI to the current limit programmed at ISET. The high-side MOSFET on-time is terminated when the currentsense signal exceeds the programmed limit. A new
Operating Conditions Charger SMPS
The MAX17085B employs a synchronous step-down DC-DC converter with an n-channel high-side MOSFET switch and an n-channel low-side synchronous rectifier. The charger features a controlled inductor current ripple architecture, current-mode control scheme with cycleby-cycle current limit. The controller's off-time (tOFF) is adjusted to keep the high-side MOSFET junction temperature constant. In this way, the controller switches faster when the high-side MOSFET has available thermal capacity. This allows the inductor current ripple and the output voltage ripple to decrease so that smaller and cheaper components can be used. The controller can also operate in discontinuous conduction mode for improved light-load efficiency.
24
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
cycle cannot start until the IMAX comparator's output goes low. U The ZCMP comparator provides zero-crossing detection during discontinuous conduction. ZCMP compares the current-sense feedback signal to 10mV. When the current-sense signal is lower than the 10mV threshold, the comparator output is high and DLC is turned off. U The OV comparator is used to prevent overvoltage at the output due to battery removal. OV compares BATT against the VCTL and CELLS settings. When BATT is 40mV/cell above the set value, the OV comparator output goes high and the high-side MOSFET on-time is terminated. DHC and DLC remain off until the OV condition is removed. CCV, CCI, CCS, and LVC Control Blocks The MAX17085B controls input current (CCS control loop), charge current (CCI control loop), or charge voltage (CCV control loop), depending on the operating condition. The three control loops--CCV, CCI, and CCS--are brought together internally at the lowest voltage clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at the CCV, CCI, or CCS appears at the output of the LVC amplifier and clamps the other control loops to within 0.3V above the control point. Clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the Compensation section). The CCI loop is compensated internally, while the CCS and CCV loops are compensated externally using a shared capacitor on the CC pin.
MAX17085B
BDIV OVP VCTL + 40mV
CSI IMAX VCSI LIMIT
CCMP LVC
R
Q
DHC DRIVER
IMIN 5mV
S
Q
DLC DRIVER
ZCMP 10mV CSSP CSIN OFF-TIME ONE-SHOT OFF-TIME COMPUTE
Figure 4. Charger Functional Diagram ______________________________________________________________________________________ 25
Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Continuous Conduction Mode With sufficiently large charge current, the MAX17085B's inductor current never crosses zero, which is defined as continuous conduction mode. The controller starts a new cycle by turning on the high-side MOSFET and turning off the low-side MOSFET. When the charge-current feedback signal (CSI) is greater than the control point (LVC), the CCMP comparator output goes high and the controller initiates the off-time by turning off the highside MOSFET and turning on the low-side MOSFET. The operating frequency is governed by the off-time and is dependent upon VCSIN and VDCIN. The on-time can be determined using the following equation:
MAX17085B
point falls below 5mV (referred at VCSIP - VCSIN). For RS2 = 20mI, this corresponds to peak inductor current to be 250mA. In discontinuous mode, a new cycle is not started until the LVC voltage rises above 5mV. Discontinuous mode operation can occur during a conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control loop, or when the charger is in constant-voltage mode with a nearly full battery pack. The charge voltage, charge current, and input currentlimit regulation loops are compensated separately and independently. The charge-current limit loop, CCI, is compensated internally, while the input current limit and charge-voltage loops, CCS and CCV, are compensated externally using a shared capacitor at the CC pin. For most applications, it is sufficient to place a 10nF capacitor from CC to GND.
Compensation
t ON =
where:
L x IRIPPLE VDCIN - VBATT
V xt IRIPPLE = BATT OFF L
The switching frequency can then be calculated: fSW = 1 t ON + t OFF
Main SMPS Detailed Description
The main SMPS of the MAX17085B consists of two independent switching regulators that generate a 3.3V and a 5V output. The regulators use the Quick-PWM control architecture for simplicity, low pin count, and fast transient response. An extended on-time feature further improves output voltage sag for high-duty-cycle applications.
At the end of the computed off-time, the controller initiates a new cycle if the control point (LVC) is greater than 5mV (referred at VCSIP - VCSIN), and the peak charge current is less than the cycle-by-cycle current limit. Restated another way, IMIN must be high, IMAX must be low, and OVP must be low for the controller to initiate a new cycle. If the peak inductor current exceeds IMAX comparator threshold or the output voltage exceeds the OVP threshold, then the on-time is terminated. The cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults. If during the off-time the inductor current goes to zero, the ZCMP comparator output pulls high, turning off the low-side MOSFET. Both the high- and low-side MOSFETs are turned off until another cycle is ready to begin. ZCMP causes the MAX17085B to enter into the discontinuous conduction mode (see the Discontinuous Conduction section). Discontinuous Conduction The MAX17085B can also operate in discontinuous conduction mode to ensure that the inductor current is always positive. The MAX17085B enters discontinuous conduction mode when the output of the LVC control
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator with voltage feed-forward. This architecture relies on the output filter capacitor's ESR to act as a current-sense resistor, so the feedback ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (270ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as sensed by the TON input, and proportional to the output voltage:
Free-Running Constant-On-Time PWM Controller with Input Feed-Forward
On-Time One-Shot
26
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
tON5 = VOUT5/VSYSTEM x tSW(NOM)/1.1 tON3 = VOUT3/VSYSTEM x tSW(NOM)/0.9 tSW(NOM) = CTON x RTON + 6.5kI where CTON = 6pF. High-frequency (~ 600kHz nominal) operation optimizes the application for the smallest component size. Efficiency trade-off due to higher switching losses is not so significant for higher output voltage rails like 5V and 3.3V. For continuous conduction operation, the actual switching frequency can be estimated by: Automatic Pulse-Skipping Mode (SKIP = 3.3V or 5V) In skip mode (SKIP = 3.3V or 5V), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing sensed across LX and AGND. In discontinuous conduction (SKIP = 3.3V or 5V, and IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error comparator threshold. Ultrasonic Mode (SKIP = GND) Forcing SKIP low (SKIP = GND) activates a unique pulse-skipping mode with a minimum switching frequency of 20kHz. This ultrasonic pulse-skipping mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the controller automatically transitions to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(SKIP)) that occurs when normally pulse skipping. An ultrasonic pulse occurs (Figure 5) when the controller detects that no switching has occurred within the last 45Fs. Once triggered, the ultrasonic circuitry pulls DL high, turning on the low-side MOSFET. This induces a negative inductor current. A negative current limit of 72mV protects against excessive negative currents when DL is turned on. After the output drops below the regulation voltage, the controller turns off the low-side MOSFET (DL pulled low) and triggers a constant on-time (DH driven high). When the on-time has expired, the controller reenables the lowside MOSFET until the inductor current drops below the zero-crossing threshold. Starting with a DL pulse greatly reduces the peak output voltage when compared to starting with a DH pulse.
45Fs (typ) INDUCTOR CURRENT
MAX17085B
fSW =
VOUT + VDIS t ON(VSYS + VCHG)
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the resistances in the charging path, including the highside switch, inductor, and PCB resistances; and tON is the on-time calculated by the MAX17085B. During heavy load transients, the main SMPS can issue an extended on-time to increase the inductor current ramp and reduce output voltage sag, thereby reducing output capacitance requirement. The extended on-time feature is ideal for high-duty-cycle conditions where the voltage across the inductor (VSYS - VOUT) is less than the output voltage. The extended on-time is twice as long as the normal on-time. A minimum off-time follows after each extended on-time. The extended on-time is allowed when the following conditions are met: U Inductor valley current at the start of the first on pulse is less than 50% of the current-limit setting. U Greater than 50% duty cycle.
Extended On-Time
Modes of Operation
Forced-PWM Mode (SKIP = 1.8V) The low-noise forced-PWM mode (SKIP = 1.8V) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while DH maintains a duty factor of VOUT/VSYS. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 15mA to 35mA per phase at 600kHz, depending on the MOSFET selection.
ZERO-CROSSING DETECTION
0
ON-TIME (tON)
Figure 5. Ultrasonic Waveforms 27
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
The current-limit circuit employs a unique "valley" current-sensing algorithm that senses the inductor current through the low-side MOSFET, across LX to AGND. If the current through the low-side MOSFET exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and battery voltage. When combined with the UVP, this current-limit method is effective in almost every circumstance. The MAX17085B includes voltage soft-start and passive soft-shutdown. During startup, the slew rate control softly slews the internal target voltage over a 2ms startup period. This long startup period reduces the inrush current during startup. Startup is always in skip mode regardless of the SKIP pin setting. When ON3 or ON5 is pulled low, or the output undervoltage fault latch is set, the regulator immediately forces DL and DH low, and enables the internal 20I discharge FET from the OUT pin to GND. When the inductor continuously conducts, the MAX17085B regulates the valley of the output ripple, so the actual DC output voltage is lower than the slope compensated trip level by 50% of the output ripple voltage. For PWM operation (continuous conduction), the output voltage is accurately defined by the following equation: V VOUT = VNOM + RIPPLE 2 where VNOM is the nominal feedback voltage and VRIPPLE is the output ripple voltage (VRIPPLE = ESR x DIINDUCTOR as described in the Output Capacitor Selection section). In discontinuous conduction (IOUT < ILOAD(SKIP)), the longer off-times allow the slope compensation to increase the threshold voltage by as much as 1%, so the output voltage regulates slightly higher than it would in PWM operation.
Valley Current-Limit Protection
PGOOD is the open-drain output that continuously monitors the output voltage for undervoltage and overvoltage conditions. PGOOD is actively held low when either output voltage is more than 250mV (typ) below the nominal regulation threshold, during soft-start, in shutdown (ON3 = ON5 = GND), and after either fault latch has been tripped. After the soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation plus 200Fs. When only one SMPS is active, PGOOD monitors the active SMPS output. When the 2nd SMPS is started, PGOOD is blanked high-Z during the 2nd SMPS soft-start plus 200Fs, then PGOOD monitors both SMPS outputs. For a logic-level PGOOD output voltage, connect an external pullup resistor between PGOOD and LDO3. A 100kI pullup resistor works well in most applications. The main SMPS features overvoltage and undervoltage fault protection that shuts down the SMPS. To prevent false trips from latching off the main SMPS, the fault latch is automatically reset after approximately 7ms. If the ON pins are still high, the respective SMPS restarts. If the fault is still present, the shutdown and restart cycle repeats. After the 4th time, the latch is permanently set and requires toggling ON3 or ON5, or pulling VCC below UVLO to start again. The charger operation is not affected by the SMPS faults. Overvoltage Protection (OVP) When the output voltage rises 16% above the fixed regulation voltage, the controller immediately pulls PGOOD low, sets the overvoltage fault latch, and immediately pulls the respective DL high, clamping the output fault to GND. The nonfaulted side also enters the shutdown state. Undervoltage Protection (UVP) When the output voltage drops 30% below the fixed regulation voltage and the inductor current exceeds the current limit, the controller immediately pulls PGOOD low, sets the undervoltage fault latch, and discharges both SMPS outputs.
Power-Good Output (PGOOD)
Soft-Start and Soft-Shutdown
Fault Protection
Output Voltage
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
Table 5. Main SMPS Fault Protection and Shutdown Operation
MODE Shutdown (ON_ = High to Low) Output UVP (Latched with 4 Autorestarts) Output OVP (Latched with 4 Autorestarts) CONTROLLER STATE Internal error amplifier target immediately resets to GND. Internal error amplifier target immediately resets to GND. After ~ 7ms timeout, the controller restarts if ON_ is still high. Controller shuts down and the internal error amplifier target resets to GND. After ~ 7ms timeout, the controller restarts if ON_ is still high. SMPS controller disabled (assuming ON_ pulled high). Internal error amplifier target immediately resets to GND. After the die temperature falls by ~ 50NC, the controller restarts if ON_ is still high. SMPS controller disabled (assuming ON_ pulled high), internal error amplifier target immediately resets to GND. SMPS controller enabled (assuming ON_ pulled high), controller ramps up the output to the preset voltage. SMPS inactive. DRIVER STATE DL and DH immediately pulled low; 20I output discharge active. DL and DH immediately pulled low; 20I output discharge active. DL immediately driven high; DH pulled low; 20I output discharge active. DL and DH pulled low; 20I output discharge active. DL and DH pulled low; 20I output discharge active. DL and DH held low and 20I output discharge active until VCC passes the UVLO threshold. DL and DH pulled low; 20I output discharge active.
MAX17085B
Thermal Fault (Latched with 4 Autorestarts) VCC UVLO Falling Edge VCC UVLO Rising Edge VCC POR
Charger Design Procedure
The selection criteria for the inductor trades off efficiency, transient response, size, and cost. The MAX17085B's charger combines all the inductor trade-offs in an optimum way using the high-frequency current-mode architecture. High-frequency operation permits the use of a smaller and cheaper inductor, and consequently results in smaller output ripple and better transient response. The charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. For optimum efficiency, choose the inductance according to the following equation: L CHG = where k = 35ns/V. For optimum size and inductor current ripple, choose LIRMAX = 0.4, which sets the ripple current to 40% of the charge current and results in a good balance between inductor size and efficiency. Higher inductor values decrease the ripple current. Smaller inductor values save cost but require higher saturation current capabilities and degrade efficiency. kVADP 2 4 x LIR MAX x I CHG
Inductor Selection
Inductor LCHG must have a saturation current rating of at least the maximum charge current plus 1/2 of the ripple current (DIL): I SAT = I CHG + IL CHG 2
The ripple current is determined by:
IL CHG =
kVADP 2 4 L CHG
The output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. As such, both capacitance and ESR are important parameters in specifying the output capacitor as a filter. Beyond the stability requirements, it is often sufficient to make sure that the output capacitor's ESR is much lower than the battery's ESR. Either tantalum or ceramic capacitors can be used on the output. Ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. Choose the output capacitor based on:
Output Capacitor Selection
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
C OUT(CHG) = IRIPPLE x k CAP-BIAS fSW x 8 x DVBATT vide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. For high-duty-cycle applications, select an LIR value of ~ 0.4. When pulse skipping (SKIP high and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT (VSYS - VOUT ) VSYSfSWILOAD(MAX)LIR
MAX17085B
where kCAP-BIAS is the derating factor for the capacitor due to DC voltage bias; kCAP-BIAS is typically 2 for 25V rated capacitors. For fSW = 1.2MHz, IRIPPLE = 1A, DVBATT = 70mV, 4.7FF is the closest common capacitor for COUT(CHG). If the internal resistance of the battery is close to the ESR of the output capacitor, the voltage ripple is shared with the battery, and is less than calculated.
Main SMPS Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: U Input Voltage Range: The maximum value (VSYS(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VSYS(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. U Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. U Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. U Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values pro-
Inductor Selection
For example: ILOAD(MAX) = 8A, VSYS = 12V, VOUT = 5V, fSW = 600kHz, 40% ripple current or LIR = 0.4: L= 5V x (12V - 5V) 12V x 600kHz x 8A x 0.4 = 1.5FH
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1 + 2 Most inductor manufacturers provide inductors in standard values, such as 1.0FH, 1.5FH, 2.2FH, 3.3FH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. Output capacitor selection is determined by the controller stability requirements, and the transient soar and sag requirements of the application.
Output Capacitor Selection
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Output Capacitor ESR The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to satisfy stability requirements. For processor core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VSTEP R ESR DILOAD(MAX) In applications without large and fast load transients, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output voltage ripple of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. Therefore, the maximum ESR required to meet ripple specifications is: VRIPPLE R ESR ILOAD(MAX)LIR The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the Transient Response section). However, low-capacity filter capacitors typically have high ESR zeros that may affect the overall stability (see the Output Capacitor Stability Considerations section). Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR SW G where: fESR = 1 2 GR ESRC OUT For a typical 600kHz application, the ESR zero frequency must be well below 200kHz, preferably below 100kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.2A = 20.8mI. One 220FF/4V SANYO polymer (TPE) capacitor provides 15mI (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic, unstable operation. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability results in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial stepresponse under/overshoot. Transient Response The inductor ripple current also impacts transientresponse performance, especially at low VSYS - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. This favors higher switching-frequency operation. The SMPSs include an extended on-time feature that reduces the output capacitor requirements due to heavy load transients. The capacitance required is also a function of the maximum duty factor and can be calculated from the following equation: C OUT L DILOAD(MAX)
MAX17085B
(
)
2
K
2VSAGVOUT
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
Common Design Procedure
100 400kHz 600kHz SCALE FACTOR (K) 800kHz 10 200kHz
The input capacitor and MOSFET selection criteria share common considerations for the charger and the main SMPS. For the following sections, VIN is VDCIN for the charger and VSYS for the main SMPS, VOUT is VBATT for the charger and VOUT5 or VOUT3 for the main SMPS, and IOUT is ICHG for the charger and ILOAD for the main SMPS. The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents: V OUT (VIN - VOUT ) IRMS = ILOAD VIN
Input Capacitor Selection
1 0.5 0.6 0.7 0.8 DUTY CYCLE 0.9 1.0
Figure 6. Scale Factor vs. Duty Cycle
where K is a function of maximum duty cycle (lowest input voltage) and switching frequency as shown in Figure 6. The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. In either configuration, choose a capacitor that has less than 10NC temperature rise at the RMS input current for optimal reliability and lifetime.
Power-MOSFET Selection
High-Side MOSFET Power Dissipation The conduction loss in the high-side MOSFET (NH) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage, and maximum output voltage in the case of the charger: V PD COND (HS) = OUT x IOUT 2 x RDS(ON) VIN Calculating the switching losses in high-side MOSFET (NH) is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: Q G(SW) C OSSVIN 2fSW PD SW (HS) = VINIOUT fSW + I 2 GATE where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2A typ). The following high-side MOSFET's loss is due to the reverserecovery charge of the low-side MOSFET's body diode:
(DILOAD(MAX) )
2
L
2C OUT VOUT
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ILOAD(MAX)LIR ILIM(VAL) > ILOAD(MAX) - 2 where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the current-sense element (low-side RDSON). Connect a resistor-divider from REF to ILIM to analog ground (AGND) to set the adjustable current-limit threshold. The valley current-limit threshold is approximately 1/10 the ILIM voltage over a 0.2V to 2.1V range. The adjustment range corresponds to a 20mV to 210mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors to prevent significant inaccuracy in the valley current-limit tolerance.
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Setting the Current Limit
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators
PD QRR (HS) = Q RR x VIN x fSW 2 pulled up by the MOSFET's gate-to-drain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS). The following minimum threshold should not be exceeded: C VGS(TH) > VIN RSS CISS Typically, adding a 4700pF between DL and power ground (CNL in Figure 7), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5I in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turnoff time (RBST in Figure 7). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
MAX17085B
The total high-side MOSFET power dissipation is:
PD TOTAL (HS) PD COND (HS) + PD SW (HS) + PD QRR (HS)
The optimum high-side MOSFET trades the switching losses with the conduction (RDS(ON)) losses over the input and output voltage ranges. For the charger, the losses at VOUT(MIN) should be roughly equal to the losses at VOUT(MAX), while for the main SMPS, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX). Low-Side MOSFET Power Dissipation For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: V PD COND (LS) = 1- OUT x IOUT 2 x RDS(ON) VIN The following additional loss occurs in the low-side MOSFET due to the body diode conduction losses: PD BDY (LS) = 0.05IPEAK x 0.4V The total power low-side MOSFET dissipation is:
MAX17085B
PD TOTAL (LS) PD COND (LS) + PD BDY (LS)
BST DH LX
(RBST)* INPUT (VIN) CBST NH L
The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency.
MOSFET Gate Drivers (DH, DL)
LDO5
CBYP
DL (CNL)* EP
NL
A low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates is used for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17085B interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). Applications with high-input voltages, long inductive driver trace, and fast rising LX edges may have shootthrough currents when the low-side MOSFET gate is
(RBST)* RECOMMENDED --THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX-TO-DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 7. Gate-Drive Circuit
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
The boost capacitors (CBST) selected must be large enough to handle the gate charging requirements of the high-side MOSFETs. Select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFETs' gates: C BST = N x Q GATE 200mV
Boost Capacitors
For example: VADP(MIN) = 17V RACIN1 = 249kI then: R ACIN2 =
(VADP(MIN)
R ACIN1
VACIN - ACOK - 1
)
= 24.1k
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (1) FDS6298 n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single FDS6298 has a maximum gate charge of 19nC (VGS = 5V). Using the above equation, the required boost capacitance would be: C BST = 1x 10nC = 0.05FF 200mV
The nearest standard resistor value for RACIN2 is 24.3kI. The ACOV threshold is then determined by: R VADP(OV) = VACIN-ACOV 1 + ACIN1 R ACIN2 where VACIN-ACOV is 2.1V (typ). Using the values in the example above, VADP(OV) is 23.7V. The relearn function is easily implemented in the MAX17085B by configuring the system to override the PDSL gate drive to the adapter and battery selector MOSFETs as shown in Figure 1. The system initiates the relearn cycle by disabling the adapter selector MOSFET and enabling the battery selector MOSFET. The MAX17085B relies on the system to monitor the battery discharge voltage. When the battery reaches its critical discharge voltage threshold, the system reenables the adapter selector MOSFET. Important: Keep ISET low during the relearn cycle. When the relearn cycle is completed, release PDSL first, wait 10ms, then enable charging. The output voltage for continuous-conduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (DIDOWN) as much as it ramps up during the on-time (DIUP). The ratio h = DIUP/DIDOWN indicates the controller's ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and VSAG greatly increases unless additional output capacitance is used.
Relearn Application
Selecting the closest standard value, this example requires a 0.1FF ceramic capacitor.
Applications Information
The input current limit should be set based on the current capability of the AC adapter and the tolerance of the input current limit. The upper limit of the input current threshold should never exceed the adapter's minimum available output current. For example, if the adapter's output current rating is 5A P 10%, the input current limit should be selected so that its upper limit is less than 5A x 0.9 = 4.5A. Since the input current-limit accuracy of the MAX17085B is P 2%, the typical value of the input current limit should be set at 4.5A divided by 1.02 4.41A. The lower limit for input current must also be considered. For chargers at the low end of the specification, the input current limit for this example could be 4.41A x 0.95 or approximately 4.19A. The minimum adapter voltage threshold is used to calculate the resistor values at ACIN: VADP(MIN) R ACIN2 = VACIN-ACOK R ACIN1 + R ACIN2
Setting Charger Input Current Limit
Main SMPS Dropout Performance
AC Adapter Detection
where VACIN-ACOK is 1.5V (typ). To minimize power loss, choose a large value for RACIN1, and calculate RACIN2.
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A reasonable minimum value for h is 1.5 for most normal regulators. With the extended on-time feature, the minimum h value of 1 can be used. Adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VOUT + VCHG VIN(MIN) = h x t OFF(MIN) 1- TSW where VCHG is the parasitic voltage drop in the charge path (see the On-Time One-Shot section) and tOFF(MIN) is from the Electrical Characteristics. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 5V, fSW = 600kHz, tSW = 1.67Fs, tOFF(MIN) = 250ns, VCHG = 100mV, h = 1: VIN(MIN) = 5V + 0.1V = 6V 1x 250ns 1- 1.67Fs
12V TO 15V CHARGE PUMP C4 0.1FF R1 100kI DX2 SKIP R2 21kI
MAX17085B
NH5 DH5 CBST5 0.1FF BST5 LX5 DL5 NL5 OUT5 DX1 C2 0.1FF C3 10nF C1 10nF
5V OUTPUT COUT5
L5
MAX17085B
Figure 8. Charge-Pump Application
Therefore, VIN must be greater than 6V for steady-state operation. Input transient sags down to 5.5V during an output load transient are acceptable due to the extended on-time feature. The MAX17085B provides a simple way to generate and valley regulate an auxiliary charge pump to provide a low-power, high-voltage (12V to 15V) supply for load switch gate drive bias. Figure 8 shows the charge-pump application circuit. The charge pump is driven by the DL pin to boost the output to the desired bias voltage (VCHG-PUMP):
VCHG - PUMP 3 x (5V - VF )
best efficiency, yet keep the charge pump output above a minimum threshold. The minimum charge-pump voltage is: R1 VCHG-PUMP(MIN) = 2.1V x 1 + R2
Charge Pump
Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: U Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. U Keep the power traces and load connections short and wide. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty.
35
PCB Layout Guidelines
where VF is the forward voltage drop of the diodes. Connect a resistor-divider from the high-voltage output to the SKIP pin as shown in Figure 8. When the voltage at the SKIP pin drops to 2.1V, which is the typical fallingedge threshold between SKIP mode and forced-PWM mode, the MAX17085B enters forced-PWM operation, recharging the bias output. This automatic refresh operation allows the MAX17085B to remain in skip mode for
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Integrated Charger, Dual Main Step-Down Controllers, and Dual LDO Regulators MAX17085B
U Minimize the main SMPS current-sensing errors by connecting LX3 and LX5 directly to the drain of the low-side MOSFET. Minimize the charger currentsense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. U When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. U Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, VCC, and OUT). U Refer to the MAX17085B evaluation kit for the layout example. Layout Procedure 1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, and COUT). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the backside opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST_ capacitor, LDO5 bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figure 1. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. 6) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location.
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Pin Configuration
PROCESS: BiCMOS
CELLS CSSP CSSN VCTL PDSL VCC CC
Chip Information
MAX17085B
TOP VIEW
ISET 31 REF 32 GND 33 ILIM3 34 ILIM5 35 SKIP 36 TON 37 ON3 38 ON5 39 DH3 40
30 29 28 27 26 25 24 23 22 21 20 CSIP 19 CSIN 18 ACOK 17 PGOOD 16 DHC
BATT
ACIN
IINP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4055-2 DOCUMENT NO. 21-0140
MAX17085B
15 LXC 14 BSTC
+
13 DLC 12 DH5 11 LX5
1 LX3
2 BST3
3 DL3
4 OUT3
5 LDO3
6 DCIN
7 LDO5
8 OUT5
9 DL5
10 BST5
THIN QFN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
37
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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